Codasip High-end processor IP and high-level design tools for RISC-Vbroad
Codasip RISC-V Solution for High-end Processor IP · Horizon Europe grant · 2022-11-01–2025-07-31
EC contribution
Total cost
Beneficiaries
About the data
Source: CORDIS (official EU open data), Horizon Europe. Framework HORIZON · call HORIZON-EIC-2022-ACCELERATOR-01 · scheme HORIZON-EIC-ACC-BF · topic HORIZON-EIC-2022-ACCELERATOROPEN-01. CORDIS record →
Objective
Codasip offers a unique combination of semiconductor processor IP based on the RISC-V open instruction set architecture (ISA) and high-level EDA tool Codasip Studio providing outstanding flexibility and 5x faster time to market. RISC-V ISA can be used for a wide variety of applications ranging from low power and low gate count embedded cores to advanced high frequency application cores. We are extending our portfolio of IP cores to include high-end high-performance compute area, complementing our cores that cover the power efficient embedded and mid range compute area: a new generation of advanced core with a 9-stage pipeline with out-of -order superscalar architecture called A90. The release of A90 will lead towards the A110 core with heavily speculative execution and an 11-stage pipeline. The design of these cores will simultaneously trigger a release of Codasip Studio processor design tool for high-end compute, including advanced features like support of out of order architectures.
Beneficiaries (2)
| Organisation | Country | Role | EC contribution | SME |
|---|---|---|---|---|
| CODASIP GMBH | DE | coordinator | €2,499,999 | Yes |
| CODASIP S R O | CZ | thirdParty | €0 | Yes |
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